Position Details

Position Id : 376747
Status : Open
Location : El Segundo, California
Duration : 6+ months
Pay Rate : DOE
Employment Type : Contract
Work Shift : Shift-1

Position Description

**US Citizenship required**

ASIC/FPGA Design Verification Engineer with UVM Experience

Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.

Requirements

Required Skills:
• 5+ years of experience
• 1-2 years of UVM tool
• Cadence Xcelium verification tool

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

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Position Details

Position Id : 376747
Status : Open
Location : El Segundo, California
Duration : 6+ months
Pay Rate : DOE
Employment Type : Contract
Work Shift : Shift-1

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